Intel is seeking a Process Engineering Director in Santa Clara, CA.
The Process Engineering Director is responsible for leading the overall performance, strategic planning and budget for all fab process areas. Additional responsibilities include, but are not limited to:
*Completing all required safety training and ensuring all work is conducted in accordance with Intel safety policies
*Establishing clear goals and challenging timelines for all area yield, process, equipment, and integration concerns
*Managing all staffing, training, technical mentorship, and personnel development for area team members
*Developing a strong business relationship with all area vendors
*Balancing cost, quality, and output with area equipment levels to meet capacity demands
*Collaborating with production and planning to continually improve area efficiency and increase output
*Partnering with area managers and other section managers to meet the needs of the fab and build strong peer relationships
*Ensuring the measurement and reduction of all process and equipment variation in the area
*Coordinating with central team, purchasing, process integration, planning, and production on new tool purchases
*Partnering with production to continually improve area efficiency, shift communication, and wafer output
*Partnering with PIE and QE teams to meet the needs of all new parts, equipment, and process changes
*Optimizing area performance to align with the business plan, strategies and goals
*Coordinating Capital Asset Utilization and TPM activities
*Partnering with other 300 mm counterparts to identify and leverage global best-known methods
*Managing the performance and professional development of direct reports
*Facilitating the technical and career development of all area personnel
*Encouraging team member engagement by setting challenging goals
*Managing projects to ensure deliverables are completed within the required timeframe
*Knowing policies and partnering closely with HR
*Ensuring area has succession plans for all key positions
*Ensuring that area scrap and excursion reduction plans are created and carried out
To learn more, or to apply online, visit the Intel website here.
